1. Field of the Invention
The present invention relates generally to memory circuitry and, more particularly, to high density and low power FeRAM devices integrated based on a read only memory (ROM) architecture.
2. Description of the Related Art
Similar to dynamic random access memory (DRAM) cells, a ferroelectric random access memory (FeRAM) cell structure includes a storage capacitance (C) to retain data and a transistor (T) to access data. Unlike DRAMs, which use paraelectrics such as silicon oxidized films or silicon nitride film for the storage capacitance, FeRAM structures use ferroelectrics. Cell information is detected by reading the change in current that results from the change in polarization charges when a voltage is applied to a cell.
As shown in prior art FIG. 1, the storage cell 10 is activated through the word-line (WL) 12, and written or read through the bit-line (BL) 14 and plate-line (PL) 16. As illustrated, the storage cell 10 includes a storage capacitor that can store a ferroelectric capacitance (CFE), to define a voltage differential “Vc.” In writing a binary digit 0 to the cell, a positive voltage (normally the full power supply, VDD) is applied to BL 14 while PL 16 is grounded and WL 12 is asserted. In writing a binary digit 1, a positive voltage is applied to PL 16 while BL 14 is grounded and WL 12 is asserted.
Reading stored data includes a sequence of: (1) precharging BL 14; (b) asserting WL 12; (c) pulsing PL 16; and (d) sensing the voltage developed on BL by a sense amplifier (not shown). Since the reading procedure is destructive, the sensed data must be written back to the memory cell 10. This will be automatically done after the data is latched in the sense amplifier by restoring PL 16 back to ground level.
A DRAM cell, which is volatile memory, is designed to keep information in only a power-on state even though it has a high operating speed. A DRAM therefore has a drawback in that the consumption of power is excessive because refreshing of data is carried out at certain time intervals to prevent data from being lost due to leakage current from a charge transfer transistor coupled to a capacitor. FeRAM cells have an advantage in that they have an operating speed similar to that of DRAMs while exhibiting reduced power consumption. That is, a FeRAM is a non-volatile memory capable of keeping data even in a power-off state, like EEPROMs and flash memories.
However, in current designs, FeRAMs are based on a standard RAM array architecture, which necessarily introduces challenges. For instance, when plate line (PL) and wordline (WL) are parallel, the design will activate all cells being controlled by the same wordline, and the respective sense amplifiers (SAs) are turned on necessarily so that the stored data of the cells will not be lost. In cases where the PL/BL are parallel and in cases of shifted bias PL, there will be only one SA ON for every I/O, however, there are respective SAs connecting to the bitlines (BL). Accordingly, current prior art techniques, such as those mentioned above, which include: (a) PL/WL parallel; (b) PL/BL parallel; and (c) shifted bias PL, all have drawbacks. Case (a) has large power consumption (i.e., high active current drain) requirements due to the need to turn all sense amplifiers along a wordline ON. And, cases (b) and (c) each require many SAs to be used, which takes up valuable chip area, although only one SA of one I/O is ON for accessing at a particular time.
Additional details regarding FeRAMs are set forth in the following publications: (1) S. Kawashima, T. Endo, A. Yamamoto, K. Nakabayashi, M. Nakazawa, K. Morita, and M.Aoki, “A Bit-Line GND Sense Technique for Low-Voltage Operation FeRAM,” Symp. VLSI Circuits 2001 Tech. Dig., pp. 127–128 (2001); and (2) L. Heller, D. Spaminato, Y. Lao, “High Sensitivity Charge-Transfer Sense Amplifier,” IEEE J. Solid State Circuits, vol. SC-11, pp. 596–601, October 1976. The disclosures of these publications are incorporated herein by reference.
In view of the foregoing, there is a need for a storage memory array architecture that provides high speed characteristics, provides low power consuming characteristics, and also provides for a dense layout for reducing chip area usage.